CPE 1510 - Computer Architecture and Assembly Language

• Compare von Neumann and split-cache Harvard computer organizations
• Describe the building blocks of computers including central processing units (CPUs), cache memory, main memory, parallel ports, and serial ports
• Write and debug assembly language programs including procedure call and interrupts
• Implement a general-purpose single clock cycle CPU for a reduced instruction set
• Implement a general-purpose pipelined CPU for a reduced instruction set
• Evaluate the performance of a CPU under multiple realistic constraints

• Integer and fixed-point binary numbers and arithmetic
• Design of combinational and sequential building blocks, arithmetic circuits, and state machines
• Design entry using a hardware description language

• Stored-program computer concept
• von Neumann 0rganization
• Split-cache Harvard organization
• Central processing unit (CPU)
• Memory and I/O pyramid
• ISO/IEC 80000 binary prefixes for memory sizing (kibi, mebi, gibi, tebi)
• ISO/IEC 80000 units for I/O sizing (kilo, mega, giga, tera)
• Instruction, address, and data busses
• Fetch-decode-execute cycle
• Instruction categories arithmetic-logic, load-store, and branch
• Execution time equation using instruction count and clock cycles-per-instruction (CPI)
• Performance analysis of instruction mixes
• Reduced instruction set computers and complex instruction set computers
• Assembly language instructions formatted as labels, opcodes, operands, and immediate literals
• Memory addresses calculated by addressing mode
• Instruction assembly to machine code stored as binary numbers
• Assembly language implementation of code blocks, do-while loops, and if-then-else constructs
• Temporary storage stacks
• Procedure call stack framing
• Assembly language procedures with and without return values
• IEEE 754 single and double precision floating point numbers
• Building block components including program counter, instruction memory, instruction decoder, two-port register files, integer ALU, floating-point unit, memory address register, memory data register, and data memory
• Single clock cycle per instruction CPU design (single-cycle microarchitecture)
• Instruction-level parallelism
• Scalar pipelined CPU design
• Scalar pipelined read-after-write data hazard management using stalls or data forwarding
• Scalar pipelined control hazard management using flush and bubble
• Scalar pipelined control hazard management using n-bit branch predictors and history tables
• Memory latency stall in scalar pipelined processors
• Reducing memory latency with cache memory
• Direct, set-associative, and fully associative cache organizations
• Performance analysis of scalar pipelined instruction mixes with and without data, control, and memory latency hazard management

• Assembly language programming and software debugging
• Design, analysis, simulation, and testing of combinational and sequential logic circuits using both paper-and-pencil and computer-aided design skillsets. 
• Testing and debugging with waveform generators, oscilloscopes, logic analyzers, and logic probes