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Nov 21, 2024
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CPE 1500 - Digital Logic3 lecture hours 2 lab hours 4 credits Course Description This course introduces combinational and sequential digital logic. Students establish skill in paper-based techniques as well as computer-aided design and analysis including schematic capture, structural and behavioral capture using a hardware description language, and simulation. Exercises require students to design, simulate, implement, and test combinational and sequential building blocks, arithmetic circuits, and finite state machines using standard logic families and programmable logic devices. Prereq: None Note: None This course meets the following Raider Core CLO Requirement: None Course Learning Outcomes Upon successful completion of this course, the student will be able to:
- Perform binary and hexadecimal arithmetic on signed and unsigned integer numbers
- Document combinational and sequential logic circuits using truth tables and waveform diagrams
- Design combinational and sequential logic circuits using Boolean algebra, Karnaugh maps, schematic diagrams, and text descriptions written in a hardware description language
- Implement, test, and analyze logic circuits using standard logic family ICs or an FPGA
- Evaluate designs under realistic constraints including timing, circuit size, power consumption, and cost
- Read and apply functional and electrical specifications provided on manufacturer data sheets
Prerequisites by Topic Course Topics
- Binary and hexadecimal signed and unsigned numbers
- Logic truth tables, operators, and IEEE Std. 91 distinctive-shape symbols
- Static electrical characteristics including power, level voltages VOH and VOL, fan-in, and fan-out
- Dynamic electrical characteristics including propagation delay, rise-time, and fall-time
- CMOS implementation of logic gates
- CMOS static and dynamic power equations
- Canonical sum-of-product equations
- Boolean algebra, K-maps, and minimized sum-of-product (SOP) form
- Gate-level circuits in NOT-AND-OR and NAND-NAND forms
- 1-of-n data selectors (multiplexers)
- Multiplexer implementations of logic equations
- Standard decoders (demultiplexers)
- Seven-segment decoders
- Full adders, ripple-carry adders, carry lookahead adders, and subtractors
- Latches and flip-flops in SR and D form
- Asynchronous and synchronous control signals
- Parallel and shift registers
- Moore and Mealy finite state machine models
- Finite state diagrams and finite state tables
- Finite state encoding using n-bit binary, Gray, or one-hot encoding
- Standard and saturating n-bit binary, modulo-n, binary coded decimal (BCD), and n-bit Gray counters
- Basic FPGA programmable device architecture
- Programmable look-up tables (LUTs)
- Structural and Behavioral hardware descriptions of combinational and sequential logic
Laboratory Topics
- Design, simulation, testing and analysis of combinational and sequential logic circuits
- Implement, test, and analyze logic circuits built using standard logic family ICs or an FPGA
- Testing and debugging using power supplies, waveform generators, and logic analyzers
Coordinator Dr. Russ Meier
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