2020-2021 Undergraduate Academic Catalog 
    
    May 20, 2022  
2020-2021 Undergraduate Academic Catalog [ARCHIVED CATALOG]

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CE 4800 - Advanced Digital Design

2 lecture hours 2 lab hours 3 credits


Course Description
This course will cover the systematic digital systems design for application-specific digital circuits on field-programmable gate arrays (FPGAs). The course will introduce top-down design processes to convert algorithms into high-level models using a hardware description language (such as VHDL or Verilog). Students will gain hands-on experience developing individual building block components, working up to designing a full digital system. This progression will focus on architecture, design methodologies, and optimization techniques. The course will also discuss hardware testing and design for testability to meet given performance specifications. (prereq: CE 1911  and CE 2820  or EE 2931  or EE 3910B )
Course Learning Outcomes
Upon successful completion of this course, the student will be able to:
  • Apply practical digital design process for FPGAs
  • Demonstrate proficiency in implementing high-level models using a hardware-description language
  • Translate software algorithm into optimized hardware architectures
  • Design digital systems with testing and testability in mind

Prerequisites by Topic
  • Fundamentals of combinational and sequential digital logic design
  • Exposure to hardware development language (e.g. VHDL)
  • High level programming language experience (C/JAVA)

Course Topics
  • Digital logic review (2 Lectures)
  • Combinational component design (4 Lectures)
  • Sequential component design (4 Lectures)
  • Digital design process (4 Lectures)
  • Design optimization (3 Lectures)
  • Hardware testing (2 Lectures)
  • Review (1 Lecture)

 


Laboratory Topics
  • Lab 1: Combinational modeling
  • Lab 2: Hierarchical modeling
  • Lab 3: Dataflow modeling
  • Lab 4: State machine design
  • Lab 5: Sequential component design
  • Lab 6: Modeling memory
  • Lab 7: Algorithmic state machine datapath design
  • Lab 8: High-level system design
  • Lab 9: High-level system verification

Coordinator
Dr. Adam Livingston



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