Feb 04, 2023  
2020-2021 Undergraduate Academic Catalog 
2020-2021 Undergraduate Academic Catalog [ARCHIVED CATALOG]

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EE 3921 - Digital System Design

3 lecture hours 2 lab hours 4 credits
Course Description
The objective of this course is to give students a solid foundation in 21st century digital systems design practices. The primary emphasis of the course is on designing a SOPC (System-On-A-Programmable-Chip). Thus, the course incorporates the use of soft processors, such as the NIOS II from Altera. Designs are specified using VHDL and simulated on a personal computer. The design is then realized on an FPGA. Real-time verification of the design using an in-system logic analyzer such as SignalTap is emphasized. The course also involves advanced projects based on a soft processor interface. Due to the project-oriented nature of the course, the syllabus is organized as a set of case studies. (prereq: CE 1911  or EE 2902, EE 2050 )
Course Learning Outcomes
Upon successful completion of this course, the student will be able to:
  • Design a complex (more than 10,000 logic elements) digital system
  • Interface to external peripherals (such as audio codecs) using various protocols (like I2C)
  • Understand the architecture behind soft processors, such as the NIOS II
  • Describe the design and verification process through written communication in the form of laboratory reports

Prerequisites by Topic
  • Design techniques for combinational and sequential digital circuits
  • Familiarity with a procedural programming language

Course Topics
  • Review the combinational logic design process
  • Review the sequential logic design process
  • Bidirectional bus interfacing
  • Algorithmic State Machine specification
  • VGA interfacing
  • External peripheral interfacing
  • Timing closure
  • Design partitioning
  • Design of digital systems as Data Path and Control Unit
  • Design of a CPU as an example of a digital system - audio codec interfacing to NIOS processor
  • Debugging

Laboratory Topics
  • Bidirectional bus interfaces
  • Timing closure
  • Soft processor interfaces
  • Finite State Machine (FSM) design using VHDL will be performed using QUARTUS II an implemented on a FPGA
  • A FSM will be designed using the ASM method. The design of the Data Path and Control Unit such as a simple microprocessor will be performed. The circuit will be simulated using QUARTUS II and implemented on a FPGA

Dr. Kerry Widder

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