Sep 27, 2022  
2019-2020 Undergraduate Academic Catalog 
    
2019-2020 Undergraduate Academic Catalog [ARCHIVED CATALOG]

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CS 493 - Advanced Digital Design

2 lecture hours 2 lab hours 3 credits
Course Description
This course introduces the concept of softcore processor design. Softcore processors are customizable systems on a chip. The students will develop custom peripherals for the softcore processor system using VHDL. Verification of the design of the peripherals will be performed by writing testbenches in VHDL and running simulations. A variety of peripherals will be designed such as a PWM component, a timer/counter component and a UART. The components that the students design will be instantiated as peripherals to the softcore processor and then downloaded to an FPGA. Test programs written in C will then be used to verify that the system functions as specified. (prereq: CE 2930 or EE 3921  or CE 2812 )
Course Learning Outcomes
Upon successful completion of this course, the student will be able to:
  • Use VHDL to describe a digital system behaviorally and structurally
  • Write a testbench in VHDL to perform simulation and verification of a digital system
  • Create a custom embedded system using a softcore processor
  • Use custom-made components written in VHDL as peripherals to a softcore process
  • Download the entire system to an FPGA and write code in C to test the design

Prerequisites by Topic
  • Combinational and sequential digital logic with VHDL
  • Computer organization and architecture

Course Topics
  • Concurrent signal assignments (2 classes)
  • Structural design (2 classes)
  • Processes and sequential statements (2 classes)
  • Finite state machine implementation (2 classes)
  • Generics and parameterized component design (1 class)
  • Case studies (6 classes)
  • Timing models for simulation (2 classes)
  • Hour examination (1 class)
  • Introduction to softcore processors (4 classes)

Laboratory Topics
  • Each instructor will assign weekly laboratory projects. All projects will utilize Quartus II for the implementation and simulation of the design. The lab exercises will utilize an Altera Development board (for example, DE1). These boards are available for checkout from the Technical Support Center

Coordinator
Dr. William Barnekow



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