CPE 4520 - Memory System and I/O System Architecture

• Diagram the memory and I/O pyramid with associated technologies identified
• Articulate primary and secondary memory characteristics
• Describe multi-level cache organization, replacement algorithms, and coherence algorithms
• Describe virtual memory held in secondary storage and its effect on performance
• Describe the use of direct memory access and its effect on performance
• Describe the logical structure and access behavior of SRAM and DRAM
• Describe the role of controller hubs in system architecture
• Describe the port structure, signals, and protocols of the ISA, PCI, PS/2, and USB busses
• Evaluate the performance of a CPU with memory and I/O under multiple realistic constraints

• Assembly language programming
• Design and simulation of scalar pipelines using a hardware description language
• Performance evaluation of central processing units (CPUs) under realistic constraints

• Memory and I/O as stored program and data repositories
• Speed and size placement on the memory and I/O pyramid  
• Multi-level on-chip cache RAM to reduce pipeline stalls caused by memory latency
• Compulsory, capacity, and conflict cache misses
• Direct, set-associative, and fully associative cache organization
• Write-through and write-back data replacement algorithms
• Cache sizing, replacement algorithm, and organization effects on cache miss rate
• Virtual memory, virtual and physical memory addresses, and paging
• Page tables, translation lookaside buffers, and virtual memory protection
• Direct memory access (DMA)
• Digital logic structure of static RAM (SRAM) and dynamic RAM (DRAM)
• Transistor structure of SRAM (six transistor memory cell, poly-load memory cell) and DRAM
• Row address and column address strobes, sense amplifiers, and restorative logic
• Logical waveforms of memory read and write cycles
• Dynamic RAM refresh cycles
• Double data rate memory (DDR)
• Memory and I/O controller hubs (north and south bridges)
• Frontside and backside busses
• Programmed and interrupt-driven I/O models
• Intel IBM PC System architecture
• Basic Input/Output System (BIOS) firmware and booting process
• Master Boot Record
• Plug-and-play technology
• Advanced Configuration and Power Interface (ACPI)
• Unified Extensible Firmware Interface (UEFI) as a BIOS replacement
• Parallel and serial communication busses
• Industry Standard Architecture (ISA) parallel bus socket, signals, and protocol waveforms
• Peripheral Component Interconnect (PCI) parallel bus socket, signals, and protocol waveforms
• PS/2 serial bus port, signals, and protocol waveforms
• Universal Serial Bus (USB) ports, signals, and protocol waveforms
• Performance evaluation of CPUs with memory and I/O systems under multiple realistic constraints