CPE 4510 - Superscalar, Multicore, and Multiprocessor Architecture

3 lecture hours 0 lab hours 3 credits

Course Description
Computer architects extend scalar pipelined processors in several ways that exploit instruction-level parallelism (ILP) and thread-level parallelism (TLP). Deep pipelines, superscalar pipelines, out-of-order instruction execution, instruction re-ordering and speculative execution are example techniques exploiting ILP. Program partitioning, scheduling across multiple computing cores, and protocols that maintain the coherency of shared memory are example techniques exploiting thread-level parallelism. These techniques raise performance by increasing the number of instructions completed per clock cycle. This course explores these topics through classroom reading, case studies, and homework exercises demonstrating mastery of terminology, concepts, logic design, simulation, and calculations.
Prereq: CPE 1510 (quarter system prereq: CE 1921 or CS 2711)
Note: None
This course meets the following Raider Core CLO Requirement: None

Course Learning Outcomes
Upon successful completion of this course, the student will be able to:

Describe how deeper pipelines affect instruction flow and performance
Describe how superscalar pipelines affect instruction flow and performance
Describe in-order and out-of-order superscalar architectures and scheduling algorithms
Describe how speculative execution affects instruction flow and performance
Describe multicore and multiprocessor architecture, program partitioning, and scheduling
Describe memory management in multicore and multiprocessor architecture
Evaluate the performance of a CPU under multiple realistic constraints

Prerequisites by Topic

Assembly language programming
Design and simulation of scalar pipelines using a hardware description language
Performance evaluation of central processing units (CPUs) under realistic constraints

Course Topics

Performance evaluation of deeper scalar pipelines
Hazard management in deeper scalar pipelines
In-order multi-issue superscalar pipelines
Out-of-order multi-issue superscalar pipelines
Reservation stations and scheduling algorithms on multi-issue pipelines
Reorder of out-of-order results to guarantee in-order register file commit
Hazard management in multi-issue superscalar pipelines
Predicated and speculative execution techniques
Flynn's taxonomy of computer architecture (SISD, MISD, SIMD, MIMD)
Vector processors
Very long instruction word (VLIW) processors
Instruction set SIMD extensions
Accelerators for workload management (GPUs and DSPs)
GPU architectures
Multicore processor architecture
Interconnection networks
Program partitioning for multicore and multiprocessor execution
Shared memory
Cache coherence protocols for invalidation, snooping, shared access, and exclusive access
Client-server model in distributed computing
Synchronization across distributed nodes
Distributed transaction models and concurrency control

Coordinator
Dr. Russ Meier

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