| |
Jan 02, 2025
|
|
|
|
|
EE 3921 - Digital System Design3 lecture hours 2 lab hours 4 credits
Course Description
The objective of this course is to give students a solid foundation in 21st century digital systems design practices. The primary emphasis of the course is on designing a SOPC (System-On-A-Programmable-Chip). Thus the course incorporates the use of soft processors, such as the NIOS II from Altera. Designs are specified using VHDL and simulated on a personal computer. The design is then realized on an FPGA. Real-time verification of the design using an in-system logic analyzer such as SignalTap is emphasized. The course also involves advanced projects based on a soft processor interface. Due to the project oriented nature of the course, the syllabus is organized as a set of Case Studies. (prereq: CE 1911 or EE 2902 , EE 2050 )
Course Learning Outcomes
Upon successful completion of this course, the student will be able to:
- Design a complex (more than 10,000 logic elements) digital system
- Interface to external peripherals (such as audio codecs) using various protocols (like I2C)
- Understand the architecture behind soft processors, such as the NIOS II
- Describe the design and verification process through written communication in the form of laboratory reports
Prerequisites by Topic
- Steady state DC electrical circuit theory
- Design techniques for combinational and sequential digital circuits
- Familiarity with the campus PC network
Course Topics
- Introduction and course overview (1 class)
- Review the combinational logic design process (1 class)
- Review the sequential logic design process (2 classes)
- Bidirectional bus interfacing (5 classes)
- Algorithmic State Machine specification (1 class)
- VGA interfacing (2 classes)
- External peripheral interfacing (1 class)
- Timing closure (3 classes)
- Design partitioning (1 class)
- Design of digital systems as Data Path and Control Unit (3 classes)
- Design of a CPU as an example of a digital system - audio codec interfacing to NIOS processor (2 classes)
- Debugging (4 classes)
- Midterm review (1 class)
- Course overview (2 classes)
- Course survey (1 class)
Laboratory Topics
- Bidirectional bus interfaces
- Timing closureSoft Processor interfacesFinite State Machine (FSM) design using VHDL will be performed using QUARTUS II an implemented on a FPGA
- A FSM will be designed using the ASM method. The design of the Data Path and Control Unit such as a simple microprocessor will be performed. The circuit will be simulated using QUARTUS II and implemented on a FPGA
Coordinator
Kerry Widder
Add to Portfolio (opens a new window)
|
|
Skip to Main Content
