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Dec 21, 2024
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CE 4930 - Computer Architecture II3 lecture hours 0 lab hours 3 credits
Course Description
Modern microprocessor architectures extend pipelined micro-architecture in a number of ways in order to exploit instruction-level parallelism (ILP) and thread-level parallelism (TLP). Deep pipelines, superscalar pipelines, out-of-order instruction execution, instruction re-ordering and speculative execution are example techniques exploiting ILP. Similarly, multiprocessor techniques such as maintaining a coherent shared memory among multiple cores are examples that exploit thread-level parallelism. These examples challenge the fundamental architectural concept of single-instruction per clock-cycle and result in circuits that improve performance and enrich the user experience. This course explores these topics through lecture, in-class problems, reading assignments, and homework. (prereq: CE 1921 or CE 2930)
Course Learning Outcomes
Upon successful completion of this course, the student will be able to:
- Describe how deep pipelines exploit instruction level parallelism and increase clock rate
- Describe how superscalar processors exploit instruction level parallelism to increase IPC
- Describe how out-of-order execution improves performance in superscalar processors
- Describe how speculative execution improves performance in microprocessor pipelines
- Compare and contrast static and dynamic speculative execution techniques
- Describe how multiprocessors exploit instruction and thread level parallelism
- Discuss classic microprocessor case studies such as the MIPS R4000, Intel Pentium, Motorola 88110, Intel Pentium Pro, and IBM Cell multiprocessor
Prerequisites by Topic
Course Topics
- No course topics appended
Coordinator
Dr. Russell Meier
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