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CE 2930 - Introduction to Computer Architecture3 lecture hours 2 lab hours 4 creditsCourse Description This course introduces the concepts of computer architecture and performance trade-offs that must be made in the design of computer systems. Topics covered include reduced instruction set computers, instruction set design options, processor implementation, pipelining and memory hierarchy. The lectures are reinforced through laboratory projects that require students to design and simulate the data path and control circuitry of a reduced instruction set microprocessor. (prereq: CE 1910, CE 2800) Course Learning Outcomes Upon successful completion of this course, the student will be able to: • use the VHDL hardware description language to implement and simulate a digital system • understand the parameters that determine CPU performance (clock cycle time, CPI, instruction count) • explain how the CPU implementation and the instruction set influence the performance parameters • implement a general-purpose register RISC CPU with instructions such as load-word, store-word, beq, addi, jump, etc. • understand the concepts of pipelining such as hazard detection, data forwarding, and branch handling Prerequisites by Topic • Digital logic design • Assembly language programming Course Topics • Introduction to the course (1 class) • Basic computer design concepts (1 class) • System performance (3 classes) • Instruction set design and related issues including operand types, addressing modes, instruction types (2 classes) • Instruction set examples (2 classes) • Design of computational circuits (2 classes) • Carry-look-ahead adders (2 classes) • Single cycle CPU implementation (3 classes) • Multi-cycle CPU implementation (3 classes) • Micro-programming (2 classes) • Pipeline implementation (4 classes) • Principles of cache design (2 classes) • Hour examinations (2 classes) • Altera Quartus Design Suite: integrated daily Laboratory Topics • VHDL design and simulation of a single-cycle MIPS microprocessor • VHDL design and simulation of a pipelined MIPS microprocessor without Coordinator Russell Meier |
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